Verilog Hardware Description Language by Chu Yu
This note covers the
following topics: Brief history of Verilog HDL, Features of Verilog HDL, HDL –
Hardware Description Language, Programming Language V.S. Verilog Verilog HDL HDL,
Time Wheel in Event-Driven Simulation, Different Levels of Abstraction, Top Down
ASIC Design Flow, Escaped Identifiers, Nets and Registers, Operators Used in
Verilog, Syntax of Verilog, Delay and Time Scales, Compiler Directives, User
Defined Primitives, Logic Strength Modeling .
Author(s): Chu Yu
104 Pages