FPGA stands for Field
Programmable Gate Array. That mouthful is simply trying to tell you that you can
program an FPGA over and over and that it is more or less
just a large array of logic gates. This PDF book covers the
following topics related to Field Programmable Gate Array (FPGA) :
Introduction, Your First FPGA Project, Combinational Logic, Sequential Logic,
Seven-Segment LED Displays and Finite-State Machines, Hello AVR, Mixing Colors
with an RGB LED, Analog Inputs, A Basic Processor, FPGA Internals, Advanced
Timing and Clock Domains, Sound Direction Detection, Lucid
Reference.
This PDF book covers the following topics
related to Field Programmable Gate Array :Frequency Trigger, Counter, Sine Package, Digital Sine, Digital Sine Top, Pwm, Modulator,
Modulator Wrapper, Design Implementation, Debugging Design, Modulator Design
Targeting Socius Development Board, Designing With Ips.
This guide reviews the historical development of programmable
logic devices, the fundamental programming technologies that the programmability
is built on, and then describes the basic understandings gleaned from research on architectures. This survey has explored many issues in
the complex and rapidly evolving world of pre-fabricated FPGA architectures.
Topics covered includes: Early History of Programmable Logic, Programming
Technologies, Logic Block Architecture, Routing Architecture, Input/Output
Architecture and Capabilities, Improving FPGAs, Emerging Challenges and
Architectures.
Author(s): Ian Kuon1, Russell Tessier and
Jonathan Rose
This note
covers the following topics: FPGA architecture, FPGA technologies, Architectures
of different commercial FPGAs, FPGA tools, FPGA implementation flow and software
involved, HDL coding for FPGA.
This note explains
the following topics: Features and Specifications of FPGAs, Basic Programmable
Devices, Features and Specifications of FPGAs, Generic Xilinx FPGA Architecture,
Virtex FPGA family name, Standard cell based IC vs. Custom design IC, Standard
cell based VLSI design flow, Simple diagram of the back-end design flow , Clock
Tree in FPGAs.