Architecture of High Performance Computers
This note will
give an introduction to designing and programming high performance processors.
Topics covered includes: Branch Prediction, renaming, precise interrupts,
Register Renaming, Wakeup, Bypass, Broadcast, Load-Store Queue, Commit, Recovery
from speculation: RRF and RRAT, SRAM vs CAM based checkpoint, ROB based OOO
processor design Little's Law, Non-Selective and Deferred Selective Replay, SRAM
and DRAM Cells, CAM Cells, Pentium Trace Cache, Date Prefetching, Cache Design
with Cacti, NUCA Caches, Routing and Flow Control, Hardware Security, Flow
Control, Coherence and Consistency, Coherence Protocols, Directory Coherence and
Atomic Primitives, Memory Consistency Models.
Author(s): Dr. Smruti R. Sarangi
NA Pages